Internal circuitry of a speech synthesis IC
Internal circuitry of a speech synthesis IC
This section describes the internal circuit configuration of a speech synthesis IC when outputting an analog signal.
① Audio data stored in memory is decoded by the decoder.
② The decoded audio data is processed through a filter.
③ The filtered audio data is fed into a DAC, which outputs an analog signal.
④ Since the DAC cannot directly drive a speaker, the analog signal is input into a high-power Class AB speaker amp (analog amp).
⑤ Finally, the Class AB speaker amp drives the speaker, producing sound.
This section explains the internal circuit configuration of a speech synthesis IC when outputting a PWM signal.
① Audio data stored in memory is decoded by the decoder.
② The decoded audio data is processed through a filter.
⑥ The filtered audio data is fed into a PWM generator, which outputs a PWM signal.
⑦ Since the PWM generator cannot directly drive a speaker, the PWM signal is sent to a high-power Class D speaker amp (digital amp).
⑧ Finally, the Class D speaker amp drives the speaker, generating sound.
Overview of Speech Synthesis Methods
To efficiently store audio data in limited memory, speech synthesis methods that compress data size are necessary. Here, we will explain various speech synthesis techniques, the compression ratio (a key metric for reducing audio size), and the characteristics of each method.
