memory_what2
Types of Memory
<Semiconductor Device Principles>
Numerous types of memory exist for Semiconductor memory Device. Basic types of memory sich as 'DRAM', 'SRAM', 'Mask ROM', 'EEPROM' and 'Flash Memory' are explained below.
DRAM
Memory Cell Structure
Consists of 1 Transistor and 1 Capacitor.
![Consists of 1 Transistor and 1 Capacitor](/documents/11303/4179182/what2_01.jpg/07c91ef6-ceaa-48f6-b32b-a559e81821a7?t=1543466578540)
Data Write Method
In the Case of '1':
- Word Line potential is High
- Bit Line potential is High
- Word Line potential is Low
![1??](/documents/11303/4179182/what2_02.jpg/bccb15bc-22b9-4092-a565-1ae392937c9c?t=1543466577737)
The state of '1'
![0??](/documents/11303/4179182/what2_03.jpg/11312adc-0c96-4082-a574-194942a00d04?t=1543466576967)
The state of '0'
SRAM
Memory Cell Structure
- 6-Transistor Cell Configuration
- 4-Transistor Cell Configuration (High Resistive Load Cell Type)
![Low Power and High Density Types](/documents/11303/4179182/what3_01.jpg/1b4dc621-174d-4b4e-8716-5187855e4ef2?t=1465523005053)
Low Power Type to the left, High Density Type to the right.
Data Write Method (see diagram below)
In the Case of '1':
- Word Line potential is High
- Assign a potential to the Bit Line (D=Low, D=High)
- The state of the flip-flop
- Word Line potential is Low
Data Read Method
In the Case of '1':
- Word Line potential OFF
- Bit Line precharge (same potential as D, D)
- Word Line potential is High
- If the Bit Line is Low the conditions will be High
- Amplified by the sense amp
![](/documents/11303/4179182/what3_02.jpg/8c8fa7e5-1711-4ce5-a6a7-07c6dd478545?t=1465523005687)
The state of '1' to the left, The state of '0' to the right. '0', '1' stored by the flip flop circuit
Mask ROM
Mask ROM Memory Cell Configuration
Adopts a NAND structure for increased integration (1 transistor cell).
![Mask ROM Memory Cell Configuration](/documents/11303/4179182/what4_01.jpg/cc60c75a-8c83-4f02-97a0-77dcfc1a02db?t=1465523006427)
Data Write Method
- Information written in the wafer process
- '1' : Ions implanted in the transistor
- '0' : No ion implantation
Data Read Method
- Word line potential of the Read Cell is 0V
- Word line potential of non-Read Cell is Vcc
- Voltage is supplied to the Bit Line
- '1' is determined if current flows
EEPROM
EEPROM Memory Cell Configuration
Consists of 2 transistor cells.
![Consists of 2 transistor cells](/documents/11303/4179182/what5_01.jpg/2be5eb04-a4cb-49a5-9fe4-f6193080e5d5?t=1465523007097)
Data Write Method
![Data Read Method](/documents/11303/4179182/what5_02.jpg/c5244a76-477e-4fb4-93dc-7aa74301cc06?t=1465523007977)
Data Erase Method
![Data Erase Method](/documents/11303/4179182/what5_03.jpg/4af01e58-9a00-4dd0-8787-68178cf887f1?t=1465523008830)
Flash Memory
Flash Memory Cell Configuration
- NAND Type
![NAND Type](/documents/11303/4179182/what6_01.jpg/57f71ac5-f263-4e62-b423-5f361da5ab9d?t=1465523009623)
4F2 area per bit when the minimum rule is F
- NOR Type
![NOR Type](/documents/11303/4179182/what6_02.jpg/e8f3a194-7f42-4e50-bb30-81a7d39bb8e6?t=1465523010420)
10F2 area per bit when the minimum rule is F
Data Write Method
![Data Read Method](/documents/11303/4179326/what6_03.jpg/726c1aba-a42f-4138-b2fe-b3a49b5540ca?t=1458245714030)
Data Erase Method
![Data Erase Method](/documents/11303/4179182/what6_04.jpg/13d2614f-b8e9-4bac-bcd4-df41fd646961?t=1465523012007)