2D/3D/CAD
- SSOP-B40 Footprint / Symbol
- SSOP-B40 3D STEP Data
It is built-in input selector of 6 stereo source and output to ADC after adjusting signal level. And built-in 2nd order post filter to reduce out of band noise and 6ch Volume circuit. It is possible to out until 5.2Vrms at maximum output. (High Voltage function) Moreover, it is simple to design set by built-in TDMA noise reduction systems.
Input (ch)
Stereo 6
ISO Input (ch)
Stereo 4
Input Gain (dB/Ad-Sw)
+23~-15/Yes
Vcc(Min.)[V]
7
Vcc(Max.)[V]
9.5
Iq[mA]
30
Outputs
6
Number of of single input
2/3/4/5
[I] Independent from Input Selector / [C] Cascade from Input Selector
I
Fader (ch/Ad-Sw)
6/Yes
Fader Range/Step (dB/dB)
+23~-79, -∞/1
Output Voltage (V, typ)
5.2
THD+N (dB)
0.003
Mixing Input
E 1
Output Noise[µVrms]
23
I/F
I2C
Power Supply Voltage (V)
7.0~9.5(VCCL) VCCL~17.8(VCCH)
Temperature (Min.)[°C]
-40
Temperature (Max.)[°C]
85
Package Size [mm]
13.6x7.8 (t=2)
Common Standard
AEC-Q100 (Automotive Grade)