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For variable delay (flexible delay time) type reset ICs, the delay pin output current (ICT) is specified by a VDD that is less than the detection voltage (in reset state), but what is the value of ICT when VDD is above the detection voltage?
Only when VDD is below the detection voltage does the NMOS transistor at the CT pin at the previous stage turns ON and discharges from the capacitor. The current is defined by ICT, and when VDD is above the release voltage the NMOS transistor is turned OFF and ICT, so it is undefined.