• For reset ICs is an output capacitor required? And if applicable what is the appropriate capacitance?
    • When the power supply (VDD) is turned ON there is an area where the output rises in the vicinity of VDD. In the case of CMOS output this rise can be suppressed by connecting an output capacitor CL to ground (for open drain output the pull-up voltage and resistance may be affected, making CMOS output not effective). The recommended capacitance is 1000pF, but the discharge current of the capacitor charging the pull-up voltage should not exceed the absolute max. rated output current or permissible loss of the package. Please note that the output capacitor may cause the reset release/detection times to be delayed, so determine the appropriate constant to ensure that no problems will occur.
    • Products: Voltage Detector with Fixed Delay Time