SiC features 10x the breakdown field strength compared with silicon, resulting in breakdown voltages in the thousands of volts. In addition, ON resistance per unit area is considerably lower, significantly improving power loss. In order to minimize the increase in ON resistance associated with higher breakdown voltages, silicon IGBTs are primarily used. However, SiC has been shown to provide superior high-speed switching performance.
- The power wiring and other considerations must be equalized to prevent an unbalanced condition regarding The chip temperature and current - Not matching The switch timing may result in damage due to overcurrent - If Vgs(on) is Not sufficiently high, Ron temperature characteristics may become negative, leading to current concentration in certain chips and possible destruction due to thermal runaway
- The ground isolation of The upper device can only guarantee The dielectric withstand voltage - A floating power supply is required for series gate voltages - When connected in series, since The temperature coefficient of The on resistance is positive, in order to prevent thermal runaway it is necessary to consider sufficient derating - taking into account product variations - When used as A single high voltage switch in series it is recommended to implement appropriate voltage dividing measures such as inserting A large resistance in parallel - The switch timing must be matched to prevent destruction due to breakdown voltage
If the gate signal wiring length is evenly configured the resistance value will range from 1-3Ω. The resistors connected to each MOSFET should be matched to the gate signal timing. However, if the wiring length is significantly different it is advisable to insert a slightly larger resistance value (~10Ω) in order to match the switch timing.
A reference board for the gate drive circuit is available (drive board designed for direct attachment to SiC modules). When connected in parallel with SiC MOSFETs, the external gate resistance is connected to each MOSFET to achieve gate signal balance.
The effects of parasitic capacitance and inductance on the board can be considered a type of LC resonance. Please confirm the following items. 1) External resistance connected to the gate drive circuit 2) Output capacitance of the gate drive circuit 3) Parasitic inductance of the gate drive circuit wiring 4) SiC MOSFET gate capacitance 5) Internal gate resistance of hte SiC MOSFET etc. When the resistance is small the overshoot/undershoot peak value will increase and prolong the ringing decay time. Also, when the capacitance is large the peak value deceases, slowing down the switching speed. Plus, a larger inductance will cause the inductance to rise.
The effects of parasitic capacitance and inductance on the board can be considered a type of LC resonance. Please confirm the following conditions. 1) Increased external gate resistance connected to the gate drive circuit 2) Smaller gate drive circuit output capacitance 3) Reduced wiring parasitic inductance of the gate drive circuit When the resistance is small the overshoot/undershoot peak value will increase and prolong the ringing decay time. Also, a higher capacitance will slow down the switching speed. And we recommend that the inductance be as small as possible.
If the drive gate voltage while ON is less than 15V it may be impossible to maintain ON operation, and when less than 14V the temperature characteristics of the ON resistance will change from positive to negative. As a result, the ON resistance will decrease at high temperatures, increasing the risk of thermal runaway. Therefore, please ensure that the voltage is greater than 15V. ROHM's TZDB series features a withstand voltage greater than 40V, preventing gate breakdown and ensuring worry-free operation. However, continuing to provide more than the rated voltage (-6V/+22V) will gradually change the threshold value due to the effects of the traps that exist on the gate oxide film interface. However, because the effects from threshold voltage fluctuations during momentary voltage surges (under 300nsec) are small, the acceptable range is actually -10V to +26V.
When the drain potential increases in the FET OFF state, there is a chance that the gate potential will rise due to the effects of AC coupling of the gate-drain capacitance. A typical example is a bridge drive connected in series. In order to prevent short-circuit damage due to erroneous ON, we recommend using negative bias. Gate potential rise can also be mitigated by adding gate-source capacitance. In addition, connecting a Miller clamp MOSFET between the gate and source can prevent an increase in gate potential through reliable short-circuit operation. However, please note that malfunctions may occur when driving the Miller clamp MOSFET due to noise.