In CMOS output type reset ICs, the output MOS transistor at the power supply side is Pch MOS, and at the ground side it's Nch MOS, meaning that the 'L' output voltage utilizes Nch operation and the 'H' output voltage Pch.
VDS is the drain-source voltage of the output MOS transistor. For open drain, this is the voltage between the output of the Nch MOS and ground. For CMOS output , it is the voltage between the Nch MOS output and ground or Pch MOS and VDD.
There is no diode between the input and output. Discharging the output capacitor is performed by turning ON the output transistor when the reset output becomes 'L' due to power supply drop. IOL listed in the datasheet becomes the discharge current capacity.
This is the voltage range supplied to the normally operating VDD pin. The reset 'L' output may not be retained if it falls below the minimum specified value (maximum specified value for the BD47x series of bipolar reset ICs).
Unless otherwise specified, the maximum value of the operating voltage range VOPL is the absolute maximum rated supply voltage. Be careful not to exceed the absolute max. ratings, even instantaneously.