For the BD45xxx/46xxx series it's 50k-1MO (VDET=2.3-4.8V), and for the BU45xxxx/46xxxx it's 50k-470kΩ (VDET=2.3-4.8V). However, this can change depending on board layout, so please perform a thorough evaluation under actual operating conditions.
In applications where the voltage is input using a resistance divider at the supply input pin, a through-current will flow instantaneously when the output logic switches, possibly causing malfunction (i.e. output oscillation). (Through current: Output switches from H to L, resulting in instantaneous current flow from VDD to Ground). Connecting a capacitor to the VDD pin reduces voltage drop, and adding a capacitor to the output pin prevents reset output chattering, making it possible to minimize ouptut oscillation. However, the reaction time may be delayed based on the capacitance. Therefore, we ask that the customer determine the constants after taking into account the set conditions. When inserting resistors (including resistance dividers), the BD52xx series is recommended.
The ER terminal is used for forced reset input. When a voltage greater than the High level is supplied, the output becomes Low. Please refer to the timing waveforms located in the technical notes for more details.
Regarding the ER terminal, a leakage pathway to the H voltage will be generated due to foreign particles (i.e. dirt, dust). In this case, even if the power supply reaches the reset detection voltage, reset cancellation will not be performed. Please refer to Item 10 in the Usage Precautions listed in the data sheet for additional details.
When the power supply voltage starts up the supply voltage will reach a point where it equals the detection voltage plus the hysteresis voltage, after which the IC will switch from L to H. To give an example, with a 3V detection reset IC, the reset voltage will switch from L to H if the voltage supplied is greater than 3V+3V×0.05=3.15V (typ.).
Please first check the 'L' level of the IC, which acts as the access point of the reset output. Below the detection voltage the reset outputs 'L', but if the pull-up resistance is too small the output voltage will not be below the 'L' level of the IC access point, preventing reset. Therefore, please refer to actual examples when determining the pull-up resistance. The maximum 'L' level of the access point is 0.7V, with a pull-up supply voltage of 3.3V. With a reset IC voltage Vdd of 1.2V and an L output current of 0.45mA, the output voltage will be 0.3V max. (Please verify the specific value with the electrical characteristic VOL) In this case the pull-up resistance can be calculated: 3.3-0.3V/0.45mA=6.7kΩ. So for a VOUT lower than 0.3V a minimum resistance of 6.7kΩ is required. However, when VDD becomes small the L output current decreases and VOUT increases, making the access point's max. 'L' level of 0.7V insufficient. It is impossible for us to know at what VDD the L level will cease to be output. Therefore, we recommend that the customer determine the final constant value by evaluating their application.