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  • For reset ICs, will the output remain at 'L' even if the supply voltage VDD falls below the operating voltage limit (VOPL)?
    • In the case of open-drain output, the detection voltage drops and when VDD falls below the operating voltage limit (VOPL) from the state where the output of the reset IC is 'L', the voltage at the pull-up location of the output resistor is output in order to turn OFF the output NMOS transistor. Also, in the case of CMOS output, when VDD drops below VOPL at 'L' output the NMOS transistor turns OFF and the output voltage is near VDD. In addition, when VDD drops below the threshold value of the PMOS transistor the output goes to high impedance and becomes undefined. In both cases (open-drain and CMOS outputs), when VDD is in the range from 0V to VOPL the output is hung at VDD and is raised, but in the event a slight rise will cause system problems we recommend connecting a capacitor at the output. Since the above operation will vary depending on the application, confirm under actual conditions.
    • Products: Voltage Detector with Fixed Delay Time  
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