System PMIC for Battery Powered Systems - BD71815AGW

BD71815AGW is a single-chip power management IC for battery-powered portable devices. The IC integrates 5 buck converters, 8 LDOs, a boost driver for LED, and a 500mA single-cell linear charger. Also included is a Coulomb counter, a real-time clock (RTC), a 32 kHz crystal oscillator and a general-purpose output (GPO).
The IC’s buck converters supply power to the application processor as well as system peripherals such as DDR memory, wireless modules, and touch controllers. These regulators maintain high efficiency over a wide range of current loads by supporting both PFM and PWM modes. They also operate at a high switching frequency of 6MHz, which allows the use of smaller and cheaper inductors and capacitors. The regulator supplying the processor core also supports Dynamic Voltage Scaling (DVS).

Data Sheet

Support Documents
Layout & Schematic Data

* This product is a STANDARD grade product and not recommend for on-vehicle devices.
Part number
Unit Quantity
Minimum Package Quantity
Packing Type
BD71815AGW-E2 Active UCSP55M4C 2500 2500 Taping Yes
Vin1(Min.)[V] 3.5
Vin1(Max.)[V] 28.0
Channel(DCDC)[ch] 5
Channel(LDO)[ch] 8
Operating Temperature (Min.)[°C] -40
Operating Temperature (Max.)[°C] 85
    • 5 buck converters:
    • 3 general-purpose LDOs
    • LDO for DDR Reference Voltage (DVREF)
    • LDO for Secure Non-Volatile Storage (SNVS)
    • LDO for Low-Power State Retention (LPSR)
    • LDO for SD Card with dedicated enable terminal
    • LDO for SD Card Interface with dedicated terminal
      to dynamically change output voltage
    • White LED Boost Converter
    • Single-cell Linear LIB Charger with 30V OVP
    • Voltage Measurement for Thermistor
    • Embedded Coulomb Counter for Battery Fuel Gauging
    • Battery Monitoring and Alarm Output
    • Real Time Clock with 32.768kHz crystal oscillator
    • 1 GPO Open Drain or CMOS Output Selectable)
    • Power Control I/O
    • 1 LED Indicator
    • I²C interface
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Technical Data
Platfrom Design Guide

The “BD71815AGWP latform Design Guide” provides design guideline which is recommended to PCB layer stack up, the components placement and the PCB routing. To reduce the risk that comes from PCB layout or parts placement, the guideline is strongly recommended to be adapted to the PCB design.

Reference BOM List

Excel: 18KB

Layout Data

Cadence Allegro: 1.6MB

Schematic Data

Cadence OrCad: 0.4MB

Schematic Data


Thermal Resistance

The definition and how to use thermal resistance and thermal characterization parameter of packages for ROHM’s integrated circuit are described in this application note.