A. Output changes will be delayed, resulting in a delay in reset detection/cancellation. Therefore, please verify that there are no adverse effects due to delayed output changes from power supply fluctuations in the actual set, and take this phenomenon under consideration when selecting circuit constants.

A. No. The entire lineup integrates hysteresis.

A. No, there shouldn't be a problem.

A. Yes, all of the products are RoHS-compliant.

A. Effects: Unexpected malfunctions may occur (but this is unlikely).
The SUB terminal:
(BU42□□/BU43□□/BU48□□/BU49□□ series)
On the chip, since the lowest potential is at V_DD, the SUB terminal is connected to V_DD.
(BD45□□/BD46□□/BD47□□/BD48□□/BD49□□/BD52□□/BD53□□ series)
On the chip, since the lowest potential is at ground, the SUB terminal is connected to ground.

A. No problems should occur.

A. The detection voltage is designed to be less than the cancellation voltage, and is verified via testing before shipment.

A. Please inquire at the nearest sales office by phone or fill out this form.

A. They can be found in the 'mounting specifications' in the external dimensions diagram by clicking on the package link on the relevant product page.
Also, please refer to the following.
BD□□□□F series/BU□□□□F series: SOP4
BD□□□□g series/BU□□□□g series: SSOP5
BD□□□□FVE series/BU□□□□FVE series: VSOF5

A. There is not diode connected between Vout and Vdd. The output NMOS current capability is the I_OL listed in the technical notes, and discharge is performed based on this characteristic.

A. This is the minimum value of the operating range of the V_DD pin.

A. Please consider this to be the absolute maximum rated value (10V for BD series and 7V for BU).
*The surge should also be within 10V or 7V

A. Regarding reset output during power supply startup, the power supply rise time will vary depending on the external load.
Because of this the minimum rated value cannot be specified. Please ensure that sufficient margin is included for transient response based on external circuitry or conditions.

A. Variations due to temperature are small, so no large fluctuations will occur. As a reference the value will decrease by about 0.1%.

A. The maximum rated currents are not specified.
It has been confirmed that in a worst case scenario with a maximum rated voltage=10V, no damage will occur even if the V_OUT pin is shorted.

A. Reference data regarding the specifications for reset recovery time is contained in the technical notes. With the BU4845, the rise time (tPLH) is 23.3µs and the fall time (tpHL) is 275.9µs, while for the BU4945 the rise and fall times are 3.5µs and 354.3µs, respectively. (V_DD=4.3V←→5.1V)
For cases where the power supply fluctuation is faster than this time the output will become delayed.
If within this reaction time the power supply recovers no reaction from the output will occur.
The output behavior may differ depending on power supply voltage fluctuations or changing conditions. Therefore, ROHM recommends that the customer ensures sufficient margins in their designs.

A. For the BU49□□ series with CMOS output, the output will be based on the surge voltage, while in the BU48□□ series with open drain output the pull-up voltage will be output continously. Regarding the reaction time in response to surges, please refer to the reference data for tPHL and tPLH on page 5 of the technical notes.

A. BD48□□/BD49□□ series: 10k-1MΩ (V_DET=2.3-6.0V)
BU48□□/BU49□□ series: 10k-1MΩ (V_DET=1.5-4.8V)
BU48□□/BU49□□ series: 100k-1MΩ (V_DET=0.9-1.4V)
However, this value may vary depending on board layout. Therefore, please verify under actual operating conditions.

A. In applications where voltage is input to the V_DD terminal via a voltage divider (resistance), a pass-through current will momentarily flow during output logic switching. This current may cause malfunctions.
(Pass-through current: Instantaneous current that flows from V_DD to ground during output H←→L switching.)
Configuring a capacitor at the V_DD terminal will reduce voltage drop, while connecting one to the output terminal will prevent output reset chatter, suppressing output vibration. However, the capacitance value will affect the reaction time, making it imperative to consider the set conditions when selecting a capacitor.
The BD48□□ series is recommended when introducing a resistor (including resistance divider circuits).

A. When V_DD falls below the operating limiting voltage (V_OPL) the output will become unstable. For details, please refer to the technical notes (Pg. 5, Fig. 14)

A. No. The output switching time can be calculated using the discharge of the input capacitor through the IC current consumption. Please estimate using the circuit current given in the electrical characteristics in the technical notes (Pg. 4, Figs. 3, 9, and 10). However, please note that if the power supply is connected to devices other than the reset IC, the total sum of all components must be taken into account when considering the discharge current.

A. The circuit current listed in the electrical characteristics in the technical notes, along with examples in Figures 3, 9, and 10 on page 4, allow estimation of the internal resistance.

A. The circuit current will vary based on the power supply voltage. Please confirm the supply voltage and internal resistance value referenced in the examples in Figures 3, 9, and 10 on page 4 and the circuit current listed in the electrical characteristics in the technical notes.

A. The circuit current will change depending on the temperature. Please confirm the supply voltage and internal resistance value referenced in the examples in Figures 3, 9, and 10 on page 4 and the circuit current listed in the electrical characteristics in the technical notes.

A. When the power supply voltage starts up the supply voltage will reach a point where it equals the detection voltage plus the hysteresis voltage, after which the IC will switch from L to H. To give an example, with a 3V detection reset IC, the reset voltage will switch from L to H if the voltage supplied is greater than 3V+3V×0.05=3.15V (typ.).

A. First, please confirm that the reset IC output is connected to the L level. Below the detection voltage the reset will output an L level. If the pull-up resistance is too small, the connected IC will not be at the L level, and therefore cannot reset. Please see below for an example.
For a circuit with an L level of 0.9V (max.), a pull-up supply voltage of 3.3V, a detection voltage of 2.7V, and a pull-up resistance of 4.7kΩ, with a reset IC V_DD of 1.5V the L output current will be around 1.0mA (0.4mA min). (Please refer to the electrical characteristics for I_OL.) The reset output level will now be calculated for V_DD=1.5V.
V_OUT (typ.)=3.3V-4.7kΩ × 1.0mA=0V, V_OUT(min)=3.3V-4.7kΩ × 0.4mA=1.42V.
With an IC with a max. L level of 0.9V, although under normal conditions at V_DD=1.5V the L level threshold is satisfied, the L output current minimum is not. However, as V_DD rises so will the L level current, which will then satisfy the minimum L level conditions. We cannot determine at what V_DD level the L level will be output. Therefore, please evaluate and determine the exact values in the actual set.

A. First, please confirm that the reset IC output is connected to the L level. Below the detection voltage the reset will output an L level. If the pull-up resistance is too small, the connected IC will not be at the L level, and therefore cannot reset.
For a circuit with an L level of 0.9V (max.), a pull-up supply voltage of 3.3V, a detection voltage of 2.7V, and a pull-up resistance of 2.0kΩ, with a reset IC V_DD of 1.5V the L output current will be around 3.3mA.
The reset output level will now be calculated for V_DD=1.5V.
V_OUT (typ.)=3.3V-2.0kΩ × 3.3mA=0V, V_OUT (min)=3.3V-2.0kΩ × 1.0mA=1.3V.
With an IC with a max. L level of 0.9V, although under normal conditions at V_DD=1.2V the L level threshold is satisfied, the L output current minimum is not. However, as V_DD rises so will the L level current, which will then satisfy the minimum L level conditions. We cannot determine at what V_DD level the L level will be output. Therefore, please evaluate and determine the exact values in the actual set.

A. There shouldn't be any problems. However, we don't know the actual startup method/conditions. Therefore, please monitor the reset output and verify normal operation.

A. A pass-through current flows during detection. The input capacitor serves to mitigate the voltage drop associated with this current. (The drop will be substantial if voltage is supplied to the IC via a voltage divider.)
The pass-through current may vary based on the customer's usage conditions, external resistance value, and detection voltage startup speed.
Once the voltage drop exceeds the detection hysteresis vibration may occur (please refer to the technical notes).
Therefore, please carefully select the resistor and capacitor that minimizes this voltage drop.

A. The output voltage at Low is determined by the output NMOS, and becomes I_OL listed in the electrical characteristics. Please refer to the L output current in Figure 4 of the technical notes.

A. The hysteresis voltage is added to the detection voltage V_DET, which becomes the detection cancellation voltage.
In measurement samples with a V_DET voltage, the hysteresis voltage ΔV_DET variation is added, resulting in the detection cancellation voltage.
For the BU48/49 series, V_DET × 0.03 (min), V_DET × 0.05 (typ), and V_DET × 0.07 (max) are specified. In addition there is a 1% variation in the V_DET voltage. Therefore, for a V_DET of 3.4V, the minimum hysteresis voltage will be 3.366 × 0.03 = 0.101V, while the maximum value is 3.434 × 0.07 = 0.2404V.

A. The recommended range is 100pF to 0.1µF. However, this may change depending on the circuit layout and other factors. Therefore, please verify under actual usage conditions.

A. Based on the reference value for Ta=-25 to 125ºC, the theoretical value will be +0.3×106. Therefore, in theory, the value will go from 6.0×106 to 6.3×106.
However, please note that these values cannot be guaranteed.

A. CCT and RCT are in F and Ω, while tPLH is in s.

A. According to the specifications listed in the data sheet, since ICT is the discharge current from the capacitor connected to the CT terminal, V_DD will become lower than the detection voltage.
For example, in the BD5223 when V_DD falls below 2.3V, for power supply voltages greater than 2.3V the capacitor at the CT terminal wil become charged. The discharge current ICT for power supplies at 3.0V will be out of specifications.

A. Although the situation will change depending on the WD signal, if WD is a pulse type usage is not recommended (since High/Low pulse detection is difficult).
If the WD signal is not a pulse type, voltage detection is possible using the configuration in the example above.

A. For part numbers BU42□□FVE-TR/BU43□□FVE-TR
the MSL is equivalent to Level 1

A. The output will become Low.

A. RCT is mainly comprised of a resistance element, which is not dependent on frequency. Therefore, please refer to the value specified in the technical notes.

A. At 2.5V the Delay Time will be: Delay=0.69×CtxRt.
Therefore, Ct=500ms/(0.69×9M)=0.08µF Ct=400ms/(0.69×9M)=0.06µF
Please select a capacitor accordingly.

A. As referenced in the technical notes for BU4245g/BU4345g, the sample tPHL (rise/fall delay times) are 275.7µs and 359µs. Please note that these are simply reference values.

A. Yes, it is possible, but the leakage current from the transistor will adversely affect the charge current at the CT terminal, resulting in unstable delay times. Please verify operation and performance under actual conditions.

A. When the output switches from L to H output chatter will be generated as a result of power supply/ground vibration. Connecting an output capacitor (on the order of 1000pF) will reduce this phenomenon.

A. The charge current at the CT terminal (approx. 10MΩ) may be affected by leakage current from the transistor. This can result in reset delay problems, including non-cancellation of reset operation. Therefore, please verify characteristics to ensure stable operation.

A. BD52□□/BD53□□ series: 50k-1MΩ (V_DET=2.3-6.0V)
BU42□□/BU43□□ series: 50k-1MΩ (V_DET=1.5-4.8V)
BU42□□/BU43□□ series: 100k-1MΩ (V_DET=0.9-1.4V)
However, this value may vary depending on board layout. Therefore, please verify under actual operating conditions.

A. In applications where voltage is input to the V_DD terminal via a voltage divider (resistance), a pass-through current will momentarily flow during output logic switching. This current may cause malfunctions.
(Pass-through current: Instantaneous current that flows from V_DD to ground during output H←→L switching.)
Configuring a capacitor at the V_DD terminal will reduce voltage drop, while connecting one to the output terminal will prevent output reset chatter, suppressing output vibration. However, the capacitance value will affect the reaction time, making it imperative to consider the set conditions when selecting a capacitor. The BD52□□ series is recommended when introducing a resistor (including resistance divider circuits).

A. RL=470kΩ is the condition during testing at ROHM and does not affect the detection voltage.

A. In a sampling of 25 pieces, the variation is -76ppm/ºC between -40ºC and +25ºC, and +26ppm/ºC from +25ºC to +85ºC. However, this data was taken from a single lot, and therefore cannot be guaranteed.

A. From actual samples, the delay time is 30µs at +25ºC, -1.2µs at +105ºC, and +1.0µs at -40ºC. However, these measurements were taken from a single lot, and therefore cannot be guaranteed.

A. When the power supply voltage starts up the supply voltage will reach a point where it equals the detection voltage plus the hysteresis voltage, after which the IC will switch from L to H. To give an example, with a 3V detection reset IC, the reset voltage will switch from L to H if the voltage supplied is greater than 3V+3V×0.05=3.15V (typ.).

A. First, please confirm that the reset IC output is connected to the L level. Below the detection voltage the reset will output an L level. If the pull-up resistance is too small, the connected IC will not be at the L level, and therefore cannot reset. Please see below for an example.
For a circuit with an L level of 0.9V (max.), a pull-up supply voltage of 3.3V, a detection voltage of 2.7V, and a pull-up resistance of 4.7kΩ, with a reset IC V_DD of 1.2V the L output current will be around 1.2mA (0.4mA min). (Please refer to the electrical characteristics for I_OL.) The reset output level will now be calculated for V_DD=1.2V.
V_OUT (typ.)=3.3V-4.7kΩ × 1.2mA=0V, V_OUT(min)=3.3V-4.7kΩ × 0.4mA=1.42V. With an IC with a max. L level of 0.9V, although under normal conditions at V_DD=1.2V the L level threshold is satisfied, the L output current minimum is not. However, as V_DD rises so will the L level current, which will then satisfy the minimum L level conditions. We cannot determine at what V_DD level the L level will be output. Therefore, please evaluate and determine the exact values in the actual set.

A. First, please confirm that the reset IC output is connected to the L level. Below the detection voltage the reset will output an L level. If the pull-up resistance is too small, the connected IC will not be at the L level, and therefore cannot reset.
Please see below for an example.
For a circuit with an L level of 0.9V (max.), a pull-up supply voltage of 3.3V, a detection voltage of 2.7V, and a pull-up resistance of 2.0kΩ, with a reset IC V_DD of 1.5V the L output current will be around 3.3mA (1.0mA min). (Please refer to the electrical characteristics for I_OL.)
The reset output level will now be calculated for V_DD=1.5V.
V_OUT (typ.)=3.3V-2.0kΩ × 3.3mA=0V, V_OUT(min)=3.3V-2.0kΩ × 1.0mA=1.3V.
With an IC with a max. L level of 0.9V, although under normal conditions at V_DD=1.2V the L level threshold is satisfied, the L output current minimum is not. However, as V_DD rises so will the L level current, which will then satisfy the minimum L level conditions. We cannot determine at what V_DD level the L level will be output. Therefore, please evaluate and determine the exact values in the actual set.

A. If the delay time setting is longer than the startup time there should be no problems. However, since the actual power supply startup method is not known, ROHM recommends that the user monitor the reset output and confirm stable operation.

A. Vout-gND does not apply to open drain output products. There should be no problems with ground shorts if a switch is connected between Vout and gND.

A. A pass-through current flows during detection. The input capacitor serves to mitigate the voltage drop associated with this current. (The drop will be substantial if voltage is supplied to the IC via a voltage divider.) The pass-through current may vary based on the customer's usage conditions, external resistance value, and detection voltage startup speed. Once the voltage drop exceeds the detection hysteresis vibration may occur (please refer to the technical notes). Therefore, please carefully select the resistor and capacitor that minimizes this voltage drop.

A. The output voltage at Low is determined by the output NMOS, and becomes I_OL listed in the electrical characteristics. Please refer to the L output current in Figure 4 of the technical notes.

A. RCT is connected to the CT terminal via V_DD. The BU42□□ series features an RCT of 10Ω (typ), 9Ω (min), and 11Ω (max). For an external leak of 1µA, there will be a drop of 11V max. at the CT terminal. As a result, it will be always OFF. Therefore, please select a delay terminal threshold voltage V_CTH that will not turn the device OFF.

A. The primary factor affecting the delay time is the delay circuit resistance RCT. In order to suppress fluctuations it is recommended that external resistance be connected to the CT and V_DD terminals. The resistance value must be a size (smaller than RCT) that is negligible compared with the RCT variation. However, the smaller the resistance the faster the delay, meaning that the capacitance at the CT terminal must be increased.

A. The hysteresis voltage is added to the detection voltage V_DET, which becomes the detection cancellation voltage. In measurement samples with a V_DET voltage, the hysteresis voltage ΔV_DET variation is added, resulting in the detection cancellation voltage. For the BU52/53 series, V_DET × 0.03 (min), V_DET × 0.05 (typ), and V_DET × 0.08 (max) are specified. In addition there is a 1% variation in the V_DET voltage. Therefore, for a V_DET of 3.4V, the minimum hysteresis voltage will be 3.366 × 0.03 = 0.101V, while the maximum value is 3.434 × 0.08 = 0.2747V.

A. The ER terminal is used for forced reset input. When a voltage greater than the High level is supplied, the output becomes Low.
Please refer to the timing waveforms located in the technical notes for more details.

A. Regarding the ER terminal, a leakage pathway to the H voltage will be generated due to foreign particles (i.e. dirt, dust). In this case, even if the power supply reaches the reset detection voltage, reset cancellation will not be performed. Please refer to Item 10 in the Usage Precautions listed in the data sheet for additional details.

A. 100µs min. Please refer to the timing waveforms located in the specifications for more details.

A. The time at tPHL is defined as 18µs (typ.).

A. A delay caused by the output capacitor component in response to reset detection and removal will be generated. Please verify operation before actual usage.

A. Please refer to the technical notes on page 2 for the H and L voltages of ER terminal.

A. From 10k to 1MΩ.
However, this will vary depending on the board layout. Please verify under actual operating conditions.

A. In applications where voltage is input to the V_DD terminal via a voltage divider (resistance), a pass-through current will momentarily flow during output logic switching. This current may cause malfunctions.
(Pass-through current: Instantaneous current that flows from V_DD to ground during output H←→L switching.)
Configuring a capacitor at the V_DD terminal will reduce voltage drop, while connecting one to the output terminal will prevent output reset chatter, suppressing output vibration. However, the capacitance value will affect the reaction time, making it imperative to consider the set conditions when selecting a capacitor.

A. When the power supply voltage starts up the supply voltage will reach a point where it equals the detection voltage plus the hysteresis voltage, after which the IC will switch from L to H. To give an example, with a 3V detection reset IC, the reset voltage will switch from L to H if the voltage supplied is greater than 3V+3V×0.05=3.15V (typ.).

A. First, please confirm that the reset IC output is connected to the L level. Below the detection voltage the reset will output an L level. If the pull-up resistance is too small, the connected IC will not be at the L level, and therefore cannot reset.
Please see below for an example.
For a circuit with an L level of 0.9V (max.), a pull-up supply voltage of 3.3V, a detection voltage of 2.7V, and a pull-up resistance of 4.7kΩ, with a reset IC V_DD of 1.2V the L output current will be around 1.2mA (0.4mA min). (Please refer to the electrical characteristics for I_OL.) The reset output level will now be calculated for V_DD=1.2V.
V_OUT (typ.)=3.3V-4.7kΩ × 1.2mA=0V, V_OUT(min)=3.3V-4.7kΩ × 0.4mA=1.42V.
With an IC with a max. L level of 0.9V, although under normal conditions at V_DD=1.2V the L level threshold is satisfied, the L output current minimum is not. However, as V_DD rises so will the L level current, which will then satisfy the minimum L level conditions. We cannot determine at what V_DD level the L level will be output.
Therefore, please evaluate and determine the exact values in the actual set.

A. There shouldn't be any problems. However, since we don't know the actual startup method/conditions, please monitor the reset output and verify normal operation.

A. Calculation is performed using a reference temp. of 25ºC. V_DET [at ambient temperature]=V_DET [at 25ºC] × {1+ (Ambient Temperature - 25ºC) × Temperature Coefficient}

A. Since internal pull-down (approx. 2MΩ) is performed, there should be no problems even if open.

A. Voltage input (FET).

A. This simply means if there is low impedance due to some external factor between the ER terminal and ground to connect a small pull-up resistance between the ER terminal and V_DD.

A. A pass-through current flows during detection. The input capacitor serves to mitigate the voltage drop associated with this current. (The drop will be substantial if voltage is supplied to the IC via a voltage divider.)
The pass-through current may vary based on the customer's usage conditions, external resistance value, and detection voltage startup speed.
Once the voltage drop exceeds the detection hysteresis vibration may occur (please refer to the technical notes).
Therefore, please carefully select the resistor and capacitor that minimizes this voltage drop.

A. The output voltage at Low is determined by the output NMOS, and becomes I_OL listed in the electrical characteristics. Please refer to the L output current in Figure 4 of the technical notes.

A. The hysteresis voltage is added to the detection voltage V_DET, which becomes the detection cancellation voltage.
In measurement samples with a V_DET voltage, the hysteresis voltage ΔV_DET variation is added, resulting in the detection cancellation voltage.
For the BU45/46 series, V_DET × 0.03 (min), V_DET × 0.05 (typ), and V_DET × 0.08 (max) are specified. In addition there is a 1% variation in the V_DET voltage. Therefore, for a V_DET of 3.4V, the minimum hysteresis voltage will be 3.366 × 0.03 = 0.101V, while the maximum value is 3.434 × 0.08 = 0.2747V.

A. No. The T_PLH function will not initiate, resulting in 'High' operation.

A. From 2k-1MΩ.
However, this will vary depending on board layout Therefore, please verify under actual operating conditions.

A. In applications where voltage is input to the V_DD terminal via a voltage divider (resistance), a pass-through current will momentarily flow during output logic switching. This current may cause malfunctions.
(Pass-through current: Instantaneous current that flows from V_DD to ground during output H←→L switching.
Configuring a capacitor at the V_DD terminal will reduce voltage drop, while connecting one to the output terminal will prevent output reset chatter, suppressing output vibration. However, the capacitance value will affect the reaction time, making it imperative to consider the set conditions when selecting a capacitor.

A. When the power supply voltage starts up the supply voltage will reach a point where it equals the detection voltage plus the hysteresis voltage, after which the IC will switch from L to H. To give an example, with a 3V detection reset IC, the reset voltage will switch from L to H if the voltage supplied is greater than 3V+3V×0.05=3.15V (typ.).

A. There shouldn't be any problems. However, since we don't know the actual startup method/conditions, please monitor the reset output and verify normal operation.

A. A pass-through current flows during detection. The input capacitor serves to mitigate the voltage drop associated with this current. (The drop will be substantial if voltage is supplied to the IC via a voltage divider.)
The pass-through current may vary based on the customer's usage conditions, external resistance value, and detection voltage startup speed.
Once the voltage drop exceeds the detection hysteresis vibration may occur (please refer to the technical notes).
Therefore, please carefully select the resistor and capacitor that minimizes this voltage drop.

A. The hysteresis voltage is added to the detection voltage V_DET, which becomes the detection cancellation voltage.
In measurement samples with a V_DET voltage, the hysteresis voltage ΔV_DET variation is added, resulting in the detection cancellation voltage.
For the BU47 series, hysteresis voltages of 30mV (min), 50mV (typ), and 100mV (max) are specified. In addition there is a 1% variation in the V_DET voltage. Therefore, for a V_DET of 3.4V, the maximum detection cancellation voltage is V_DET max (3.434) + 0.10 = 3.534V.