Short for Electrically Erasable Programmable ROM, EEPROMs are a type of non-volatile memory that allows data to be written to each address via electric signals.
ROHM EEPROMs are capable of an industry best 1 million rewrites and retains data for up to 40 years. ROHM's unique double cell technology has been incorporated into the entire lineup, resulting in remarkably high reliability (zero accidental defects).

Data retention is guaranteed for 40 years and has no relationship with the number of rewrites (1 million times). For example, even after the 1 millionth rewrite data retention is ensured for 40 years.

Please note that the actual value of each depends on the temperature conditions. For official requirements, please contact ROHM Sales.

A serial 2-line bus capable of 400kHz operation, it is the de facto standard interface and is widely used in digital consumer electronics, Bluetooth modules, and large household appliances.

A serial 3-line bus capable of 5MHz operation, it is geared towards high-speed communications and is used primarily in vehicles, wireless LANs, DVCs, DSCs, and the like.

A serial 3-line bus capable of 2MHz operation, it is mainly used in vehicles, HDDs, and motherboards.

ROHM's unique high-reliability memory cell construction.
Generally, with competitors, one memory cell is allocated to each bit, resulting in data corruption if the memory cell becomes defective.
ROHM, on the other hand, allocates two cells for each bit. If one cell becomes defective the other takes over, preventing data corruption, protecting the customer's important data.

This is when a defect occurs by chance in a memory cell during normal operation, resulting in memory corruption.
There are limitations on the number of times an EEPROM memory cell can be rewritten. ROHM guarantees the highest number of rewrites: 1 million times. Companies normally do not normally guarantee a chance defect will not occur within a number of times - they only confirm that all bits are normal at shipping.
ROHM has developed double-cell construction to reduce the rate of chance defects for greater data reliability.

The land pattern can be found in the external dimensions under mounting specifications by clicking the 'package' link on the relevant product page.

In addition, please refer to the following.

Please contact your nearest sales office by phone for any questions or fill out and submit an inquiry form.

No, not officially.

Please note that we cannot handle discontinued products. We ask that you look into replacement part numbers. Please refer to the discontinued part number list.

Although 100% compatible products are not available, please consider the following functionally-compatible series.
Data sheets are also available for download.

The built-in low-voltage write error protection circuit (LVcc circuit) is activated, preventing writing.
Power ON precaution: Please start up the Power On Reset (P.O.R.) circuit to ensure normal operation.

The data at the designated address will be corrupted. In this case please perform a rewrite. Data at non-designated address should be ok.

A function that resets the IC internally when the power is turned ON. When the power is turned ON the internal IC circuits and set pass through an unstable low voltage region as the Vcc rises, making it important to internally reset the IC during power up. The recommended conditions for operating the P.O.R. circuit are indicated the data sheet.

It refers to each address.

It means that each bit is guaranteed to hold data for 1 million rewrites. It does not imply the number of rewrites to the IC.

Note 1: The number of rewrites depends on the operating temperature conditions. Please consult with the Business Department for information on data reliability.

Note 2: There is no relationship between the data retention period and the number of rewrites.

Yes, it is possible.

In an EEPROM, after 1,000,000 writes the charge accumulation at the floating gate of the memory cell becomes difficult, making write operations impossible. Cells that cannot hold a charge will be set at 'L'.

Data is guaranteed for 40 years after the last rewrite has ended.

I²C BUS
  Write time is defined as the time it takes to write one byte/page.

SPI BUS
  Write time is defined as the time it takes to write one byte/page.

Microwire Bus (BR93L□□ Series, BR93H□□ Series).
  Write time is the time it takes to write one byte in one Write cycle (WRITE) as well as the time to write all addresses in a single Write All Addresses cycle (WRAL).

Operation at 100kHz max. is called STANDARD MODE, while FAST MODE indicates operation at 400kHz max.
Conditions: 1.8VVcc<2.5V (100kHz max.), 2.5VVcc 5.5V (400kHz max.)

NC terminals are not connected internally. Therefore, they can be connected to either Vcc or ground without causing problems.

The products utilize I²C BUS I/F, eliminating the need for slave address settings.

Because of this terminals A0, A1, and A2 are used. However, since 4kbit/8kbit/16kbit are utilized for Word Address settings (for details on each capacity refer to pg. 7 of the technical notes under Device Addresses), the pins are considered NC, making it OK to connect them to Vcc or Ground.

Yes, problems will occur. Please do not leave these open. The A0, A1, and A2 terminals indicate device addresses. Only when the pins' H/L condition agrees with serial input to the A0, A1, and A2 device addresses from SCL and SDA will the selected EEPROM be recognized and normal operation performed.
If the A0, A1, and A2 terminals are open, the terminal conditions cannot be set, preventing agreement of the device addresses and, subsequently, operation.

There should be no problems concerning data reliability provided that writing was performed under recommended operating conditions.

For additional information on reliability test items, please visit ROHM's EEPROM page by clicking here.

A large pull-up resistance at the input pin allows for smaller pulses during startup. However, the rise and fall of the input signal becomes slower, making it necessary to consider the timing characteristics during operation.

Yes, a resistor is necessary to prevent data collisions between the microcontroller DI/O output and EEPROM DO output. Please note the following 2 points.

1. 1 clock cycle reading the address data at A0 via a Read command
   Inputting an address data A0=1 causes a collision with the dummy bit output of '0' , resulting in the generation of pass-through current.
2. CS=H timing after a Read command
   During command input after a Write instruction, while the microcontroller DI/O output is at 'L', the CS input starts up and a Ready output 'H' is output from the DO terminal, resulting in generation of a pass-through current path.
   At this time since DI=H, SK=H is recognized as the start bit during CS input rise, please make SK=L.

The page select bit indicates the bit at the top address.
The address indicator bit is set in the 8 bits between WA7 to WA0 within the address command. However, since a total of 256 combinations are possible, for EEPROMs greater than 4kbits the address indicator bit is assigned within the Slave address.
Therefore, for the page selection bit please handle the expansion of WA7-0 considering the following.

BR24L04-W　　　PS　→　WA8
BR24L08-W　　　P1　→　WA9　　P0　→　WA8
BR24L16-W　　　P2　→　WA10 　P1　→　WA9　　P0　→　WA8
(Reference)

Type	No. of addresses	No. of required bits	Indicator address	Bit name
BR24L02-W	256	8		WA7 to WA0
BR24L04-W	512	9	PS	WA7 to WA0
BR24L08-W	1024	10	P1,P0	WA7 to WA0
BR24L16-W	2048	11	P2,P1,P0	WA7 to WA0

For an input voltage at an intermediate potential, the determination between an H input and L input at the terminal is unclear.
Yes, hysteresis is included in the input circuit and is typically 0.2V.

That ROHM EEPROMs comply with the RoHS Directive.

Please refer to ROHM's EEPROM page for details.